Hi again Noel!
If so then, I can definitely say it was the original ROM that web bad somehow (but good enough to run the tests, which is what bugs me).
My own thinking having observed this result myself before (RAM Test failure apparently corrected by replacing the ROM) goes like this:
During the QL initial start-up sequence until the end of the RAM test phase, the only interaction between the CPU and the rest of the hardware is:
a) Reading the ROM (ROMOE active, RD)
b) Writing to DRAM (ROMOE deactive, WR)
c) Reading from DRAM (ROMOE deactive, RD)
d) A few writes/reads to the ZX8301 display/DRAM controller registers
The second ULA (ZX8302) is not accessed until after the RAM test and on a basic QL, there isn't anything else directly connected to the CPU bus, so nothing else to interfere (yet).
If we assume that the DRAM and associated databus buffer/address multiplexors and the ZX8301 itself are all good - indicated by the fact that after replacing the ROM ICs with your EPROM board allows a successful start-up - and that the RAM test fails during the first phase (white-screen), then something is interfering with the ability to read-back the test values just written to DRAM.
If either of the two default ROM ICs fail to deactivate/make high-impedence their datalines between valid ROM access (when ROMOE is active), then it is conceivable that what the CPU is trying to write (and read-back) to DRAM is contending with whatever the ROM is currently holding on the databus.
Its just speculation, but sufficiently satisfied my curiosity when I first thought it through. Others on the forum with far greater reasoning skills than I may have a better explanation!
If you can be bothered, you could test this theory by replacing the ROM ICs from the Issue 6 (white-screen) in to the Issue-5 (green screen), and see whether the error moves from second phase (green) to first (white).
