Hi,
I have been using the QubIDE GALs in a project and got to a good place. I'd like to widen it out from latching 8 bits to make 16-bits to being natively 16-bit. Double the throughput.
I can't find the equations that make the V2 GALs *anywhere*. I have looked for several hours now. I also tried decompiling the fuse maps with Opaljr but the results don't compile back to working GALs so that's a bad place to start off from.
Does anyone have equations for the v2 GALs?
Any pointers appreciated.
QubIDE V2 equations
Re: QubIDE V2 equations
Mame has a tool, "jedutil", to decompile gals .Jedec file that had use in the pass with very good results, try it.
Re: QubIDE V2 equations
Hi Dave,
not sure about V2. At https://omega.webnode.page/products/product-1/ there are GAL sources in "qubide_gals.rar" which might be worth looking at. If I was you, I'd rewrite the logic from scratch though, using a PLD.
Good luck, Peter
not sure about V2. At https://omega.webnode.page/products/product-1/ there are GAL sources in "qubide_gals.rar" which might be worth looking at. If I was you, I'd rewrite the logic from scratch though, using a PLD.
Good luck, Peter
Last edited by Peter on Tue Sep 02, 2025 5:29 pm, edited 1 time in total.
Re: QubIDE V2 equations
Hi Dave -
If you are making a 16 bit version of Qubide - then technically you can eliminate or greatly simlify the logic in one GAL - as you basically just need to drive a 16 bit transceiver when the qubide address is detected, the remaining GAL - which handled buffering of reset and performing the translation of the QL's address lines to the CS1 and CS3 selects on the IDE interface are pretty much all that's required. A project I am working on will be using this approach.
If you are making a 16 bit version of Qubide - then technically you can eliminate or greatly simlify the logic in one GAL - as you basically just need to drive a 16 bit transceiver when the qubide address is detected, the remaining GAL - which handled buffering of reset and performing the translation of the QL's address lines to the CS1 and CS3 selects on the IDE interface are pretty much all that's required. A project I am working on will be using this approach.
Re: QubIDE V2 equations
And some!
Not going to set any of the big records, but it will be quick hopefully.
It will have a 16 bit bus - for ROM, RAM, Video, and IDE.
Re: QubIDE V2 equations
Initially 68SEC000 in 16-bit mode at 30 MHz, running now.
I have now obtained the equations I needed. Yes, I will be able to eliminate a lot of the byte to word shuffling. The endianness reordering option I was particularly interested in. Also, if/how it approached IOREADY to get support for PIO 4 and 5. The system can manage speeds where PIO 4 offers notable benefits in transfer speed.
Thank you everyone for your tips and pointers.
The resulting equations, .jed and schematic will be open sourced once I have recovered the design cost.
I have now obtained the equations I needed. Yes, I will be able to eliminate a lot of the byte to word shuffling. The endianness reordering option I was particularly interested in. Also, if/how it approached IOREADY to get support for PIO 4 and 5. The system can manage speeds where PIO 4 offers notable benefits in transfer speed.
Thank you everyone for your tips and pointers.
The resulting equations, .jed and schematic will be open sourced once I have recovered the design cost.