My current QL accelerator project

[napsternds]

Hi all, I decided to follow Peter's advice and not bother with making a 68000 board for the QL, I went straight for a PiStorm in the expansion socket, once it's working I'll do a CPU Socket version.

I am trying to make the minimum of changes to the PiStorm source code to make it 8 bit and to the Verilog CPLD code.

Once it's running, it I will need to strip out the Amiga stuff and make virtual HDD, RTG and Network stuff for the QL.

I had to 5 boards made if anyone else would like to join in the fun, message me.

Please let me know if you can see anything wrong on the schematic that I may not have thought of,
I am not sure how I will disable the 68008, as there is no Halt on the expansion port but I guess I could just take it out altogether.

WillQL PiStorm Schematic.pdf

board.jpg

Great project. Good luck. I'd love joining in the fun, but my soldering skills are (well, are not). I will follow your progress

[tofro]

Please let me know if you can see anything wrong on the schematic that I may not have thought of,
I am not sure how I will disable the 68008, as there is no Halt on the expansion port but I guess I could just take it out altogether.

You can disable all 68k CPUs by pulling the /BR (Bus Request) signal to low. If you do this dynamically, the CPU will "answer" by setting /BG (Bus Grant) low and shutting down all bus activity.

The exact behavior is described in the CPU manuals.

[techfury]

You can disable all 68k CPUs by pulling the /BR (Bus Request) signal to low. If you do this dynamically, the CPU will "answer" by setting /BG (Bus Grant) low and shutting down all bus activity.

The exact behavior is described in the CPU manuals.

tofro, I'm curious.

If one were to develop a hypothetical expansion with a ROM replacer (using the good old trick of forcing DSMCL high through a diode when the address range matches)... that requires some time for the "ROM" to be initialized (let's say it's really SRAM and some steps are taken in hardware to load the ROM image into SRAM), would holding BR at power-on reset and then releasing it once the "ROM" is ready suffice? I had initially thought of keeping DTACK floating but I suspect BG keeps the address/data bus in a more "idle" state...

[tofro]

You can disable all 68k CPUs by pulling the /BR (Bus Request) signal to low. If you do this dynamically, the CPU will "answer" by setting /BG (Bus Grant) low and shutting down all bus activity.

The exact behavior is described in the CPU manuals.

tofro, I'm curious.

If one were to develop a hypothetical expansion with a ROM replacer (using the good old trick of forcing DSMCL high through a diode when the address range matches)... that requires some time for the "ROM" to be initialized (let's say it's really SRAM and some steps are taken in hardware to load the ROM image into SRAM), would holding BR at power-on reset and then releasing it once the "ROM" is ready suffice? I had initially thought of keeping DTACK floating but I suspect BG keeps the address/data bus in a more "idle" state...

Hmm. Don't know. The BR/BG mechanism isn't a "freeze-and-drop-dead" activity, but rather an orderly shutdown of the CPU. The CPU finishes its current bus cycle, asserts /BG and shuts down, releasing the bus. What happens after a reset when /BR is already asserted (CPU wants to fetch the initial PC and stack pointer from 0), I don't know (And the manuals don't cover this case). "Dumb" devices grabbing the bus via /BR should probably consult additional signals (like /AS) to see that the current bus cycle is really finished. In your case, I don't see why there shouldn't be (or, rather, see some strong reasons for) a RESET once the "ROM" has finished initializing.

[techfury]

Just use RESET because we don't know if it'll properly resume the initial SP/PC fetch operation... that makes sense. Thanks!

[Pr0f]

The Gold and SuperGold card both just strap the /BR line to ground - no fancy hardware - the 68008 in the QL obliges after reset by doing the right thing and just taking itself off for a long holiday

[tofro]

The Gold and SuperGold card both just strap the /BR line to ground - no fancy hardware - the 68008 in the QL obliges after reset by doing the right thing and just taking itself off for a long holiday

Well, with a GC/SGC, it never needs to wake up again, which makes it relatively arbitrary in what state it's dismissed. Techfury's use case is maybe a bit different, because the CPU needs to come back to an orderly state. But I'd also try the simple solutions first

[techfury]

Well, with a GC/SGC, it never needs to wake up again, which makes it relatively arbitrary in what state it's dismissed. Techfury's use case is maybe a bit different, because the CPU needs to come back to an orderly state. But I'd also try the simple solutions first

That's correct, the 68008 needs to proceed with its usual boot process.

If you're curious as to why I asked... I've been at work on and off on yet another Trump Card clone, but this time, it uses the VHDL WD1772 clone core from the Suska ST clone as opposed to an actual 1772. Still not tested on real hardware yet, but it is able to successfully run through a test bench consisting of seeking, formatting tracks, reading, and writing sectors. (Writing a simulated floppy drive is... interesting for sure.)

I've managed to fit it in a $10 Lattice iCE40HX4K along with QL-SD and still have about two thirds of the logic cells unused. My thinking here is that since we're already stuffing SPI flash for the FPGA bitstream... why not use the rest of it for other functions? Perhaps it could provide a ROM switcher by copying from SPI flash to SRAM during power-on initialization...

[bwinkel67]

Hi all, I decided to follow Peter's advice and not bother with making a 68000 board for the QL, I went straight for a PiStorm in the expansion socket, once it's working I'll do a CPU Socket version.

I am trying to make the minimum of changes to the PiStorm source code to make it 8 bit and to the Verilog CPLD code.

Once it's running, it I will need to strip out the Amiga stuff and make virtual HDD, RTG and Network stuff for the QL.

I had to 5 boards made if anyone else would like to join in the fun, message me.

Please let me know if you can see anything wrong on the schematic that I may not have thought of,
I am not sure how I will disable the 68008, as there is no Halt on the expansion port but I guess I could just take it out altogether.

WillQL PiStorm Schematic.pdf

board.jpg

Oh cool...great that you've gotten this far. I'm interested, depending on what it entails, i.e. if I have the tools/skill, not much experience with SMD soldering but through hole I've done lots of. I'll be recapping my Amiga 600 in May so that'll be good experience.

Are you on the PiStorm Discord server? Might as well finally ad a Sinclair QL channel!!!

[Peter]

Please let me know if you can see anything wrong on the schematic that I may not have thought of

U7B has only inputs.