Networking the QL and ZX Spectrum - updated guide (Part-1)

[martyn_hill]

Hi everyone!

With the recent developments in the Spectrum Next/QL-Core to add QLAN compatible networking, it was time to update the guide to QL and Spectrum networking - hereby attached as v2.2.

This is still 'Part-1' of a 3-part series of articles on the topic, but with added material, a bunch of corrections and generally streamlined over the earlier versions posted on the forum - with thanks to my 17-yr old son, Ale, for his proof-reading and suggestions to simplify some of the text!

With that update out of the way, I'll now start in earnest on parts 2 and 3...

Feedback and questions welcome, as ever.

Martyn.

[Derek_Stewart]

Hi Martyn

The update to the Networking Guide is really good, well done.

I am sorry to say I have been a little slow on getting the update QLUB interface out. I will get this done ASAP as it is a good addition to Q68/QL connection to QL emulators.

I will have a go at building the Spectrum Next Joystick/NET Adapter and get it connected to the Q68.

[Peter]

Many thanks Martyn,

excellent work. Your document will be very helpful for me, in case I find the time to implement FPGA hardware support for QLNET someday. Depending on the exact architecture, a potential new 68060 machine might not allow a Q68-like "fast SRAM" workaround for SDRAM related latencies, in which case hardware needs to do some of the work in the background to satisfy the timing requirements.

Another thing I can not get out of my head is to do QL networking over a LVDS physical layer, which would provide enormous speeds. Not sure I should introduce yet another playground in addition to Ethernet and singlewire QLNET, but it is tempting, because most FPGAs have LVDS onboard.

All the best
Peter

[martyn_hill]

Hi Derek

Thanks for the feedback and good luck with the QLUB Adapter builds!

I will have a good at building the Spectrum Next Joystick/NET Adapter and get it connected to the Q68.

Having built a few different versions of the Joy2NET adapter, the main difficulty has been trying to squeeze the components in to as small a project-box as possible and making the connections tidy.

With the design of a proper PCB rather than the prototyping boards I've used so far and using some compact wire-to-board connectors (such as the smaller JST variety), it should be possible to make a more 'production-ready' version.

[martyn_hill]

Hi Peter!

Thanks for the feedback

...in case I find the time to implement FPGA hardware support for QLNET someday.

I've been giving some thought recently to how the most timing-critical aspects could be re-implemented in hardware - I intend to share my ideas in a future article, but would certainly welcome discussing how it could be done in FPGA 'someday'!

Another thing I can not get out of my head is to do QL networking over a LVDS physical layer...

Intriguing! Given the up-take of the QIMSI Gold and the availability of its LVDS connection, it would certainly make an interesting solution for connecting suitably equipped QLs!

[Martin_Head]

Hi Martyn,

In your guide, in the Trouble shooting Network problems section. You mention that issue 5 QL's can have irregular timing problems.

I think that one of my QL's may have this problem. Could this problem be fixed by a special version of the Toolkit 2 ROM, that could compensate for the irregularities, or are they just too irregular to handle.

[martyn_hill]

Hi Martin!

To be honest, if the ULA access contention of your Iss5 turns-out to be the primary cause of the problem, I don't think tweaking the Timing Constants or the TK2 code itself will fully overcome the issue, though if anything would help it might be to very slightly reduce the timing-constant 'ndt_rdly'.

I assume no (super)Gold Card is fitted and that your TK2 is in ROM, in which case any changes to that timing-constant requires to patch (a single byte) and re-flash your EEPROM. And it may still not help a great deal.

To get my Iss5's NET working more consistently, I ended up hacking the board and adding a GAL to effectively bring the 8302 on to the CPU side of the bus, like it became in later issue boards. A nasty hack, but effective...

We could pick-up this thread via email, if you do want to pursue it.

M.

[bwinkel67]

To be honest, if the ULA access contention of your Iss5 turns-out to be the primary cause of the problem, I don't think tweaking the Timing Constants or the TK2 code itself will fully overcome the issue, though if anything would help it might be to very slightly reduce the timing-constant 'ndt_rdly'.

You had tweaked TK2 timings to get my QL to talk successfully to my Spectrum. Was that a similar issue? I'm not quite sure what issue board I have. It's a US one where it says "US 5" on the back of the motherboard.

[Derek_Stewart]

Hi,

I use Issue 5, 6, 7 QL all networked to the Q68, QXL and QL emulators on Linux PC via QLUB, with no problem.

The only, non working QL network station is a QL with the QLion board. But this mighf be a timming issue.

When I build the Spectrum Next JoyNet interface, should network to its nearest rivial...

[Peter]

Hi Martyn,

Another thing I can not get out of my head is to do QL networking over a LVDS physical layer...

Intriguing! Given the up-take of the QIMSI Gold and the availability of its LVDS connection, it would certainly make an interesting solution for connecting suitably equipped QLs!

The LVDS connection of QIMSI Gold is normally used for video, and I'm not sure if the former 6 pin VGA connector leads to suitable FPGA pins. The resistors in the VGA lines would pose an additional problem. So while an LVDS network connector is quite easy for a new or redesigned device, I'm not sure about existing ones.

Before we put further thought into this: Wouldn't a third physical network layer in addition to Ethernet and QLNET fragment development and user base too much?