QL-Lion (QLion) card project

[lliont]

the "fpga replacement" uses both the expansion port and the ula socket, there is a small board connected to the main board by a wire that plugs into the ula socket.
QLion is just an expansion card.

[bwinkel67]

the "fpga replacement" uses both the expansion port and the ula socket, there is a small board connected to the main board by a wire that plugs into the ula socket.
QLion is just an expansion card.

Oh interesting. Is there then a difference (advantage) in going with this two-board expansion versus QLison and CPLD ZX8301? (i.e. speed maybe?)

[lliont]

No, also if you have a working zx8301 there is no reason to use a ula replacement board with the QLion card.
Also note that when you use QLion card the QL video port is not working, you get the output from the card's VGA port.

[lliont]

About microdrives and the NET.
In order for the microdrives to work correctly and because of the increased speed the FSLOW command has to be used that lowers the QLion speed before loading from the microdrives and optionaly use the FFAST command after to return to high speed.
This FSLOW command is also usefull for playing games that otherwise whould be too fast.
A better way to deal with it is to patch the Minerva and/or the JS binary in the card's flash. I haven't done this yet (and I don't know how to do it yet).

[martyn_hill]

Hi Leon!

Another excellent solution

I'd be happy to explore the nec essay adjustments to the MDV and NET access primitives in QDOS to match the higher CPU speeds of the QLion card.

I would however need to know a bit more about the effective CPU clock & contention timings when accessing the 8-bit bus.

Also, if you did implement a fast timer/counter, how to access that and it's parameters.

I have made such adjustments to both NET and MDV routines to work with the Q68's 40MHz timer/counter, so have a head start in this area

Warm regards,
M.

[lliont]

Thanks, I will contact you by email.
I have a fast counter that is for general use, so I will make one dedicated to the mdv routines that wouldn't be changing by a user.

[Peter]

I have a fast counter that is for general use, so I will make one dedicated to the mdv routines that wouldn't be changing by a user.

It might be worth considering a 32 bit, 25 ns resolution timer of you have space for that in your FPGA.
Used on Q68, Qzero and QIMSI Gold, it might be considered sort of a "standard" by now.
Compatibility would simplify software support when it comes to QLNET, ethernet, microdrives or even YM sound.

[lliont]

thanks, I have space and I'll implement one.

Done! 32bit counter 40Mhz at 0x800060

[Peter]

Any chance to place it at $1C060 ? Then it would be the exact same.
Also my newer machines have a hardware identification register at $1C000, where 0=Q68, 1=Qzero, 2=QIMSI.
If you like, you could set numbers from 8 onwards.

[Pr0f]

Any chance to place it at $1C060 ? Then it would be the exact same.
Also my newer machines have a hardware identification register at $1C000, where 0=Q68, 1=Qzero, 2=QIMSI.
If you like, you could set numbers from 8 onwards.

Interesting - so what's happening with 3-7 future products?