"what-if" QL extended graphics

[Nasta]

And it is a bit more complicated, don't forget that ula in this bus has to check for the dsmc suddenly going high again by an expansion card and abort it's operation. So it can not function arbitrary fast or it will not give the card access.
If it controlled all the ram and not the 128K it could ignore the dsmc for the ram range.

The ULA does not check for this and really can't, if it sees it low by a certain half clock of the CPU, it will start the DRAM access if possible. The best you can do is prevent CAS from being generated if it is not low after that to prevent RAM corruption.
You have to work at 2x CPU frequency since the CPU itself works in half clock cycles.
Keep in mind that DSMCL is actually CPU /DS so the circuit that has to externally pull DSMCL up has to be able to decode that the address does not belong to the ULA and pull up DSMCL from the address (and possibly RDWL) setup time before DSL goes low. If you are generating this asynchronously and as a result there is a chip enable and/or output enable generated from it at some point, the critical path happens on read because DSL gets pulled down by the CPU at the same time as ASL so there is about 1/2 clock of time (at best!) if every signal is fairly equally loaded. On write it is almost impossible not to satisfy it as the setup time is about 1.5 clock cycles. If you generate a chip select and then deactivate it before something is asynchronously read, the data may appear on the bus and then disappear before the proper device supplies data, possibly resulting in a very short bus contention.
But if an asychronous signal is generated which result in some state change in the hardware that was supposed to be addressed but then was not, all sorts of unpredictable behavior can happen.
The best one can do is once the DSMCL signal goes low, not to act until the last possible moment based on the required timing you are about to address within the ULA domain. Even then, there is just so much you can do to mitigate for someone else's badly designed hardware...

[Nasta]

And with RASL/CASL of the QL's DRAM inactive, the multiplexer could be switched faster. I might overlook something, but I think even zero waitstates is doable despite the multiplexers.

Fortunately the mux select and output enable lines are separate from RAS and CAS, as well as the DRAM WE. That being said you must not completely stop toggling RAS because it is used for the internal charge pump to negatively bias the substrate of the DRAM chips, without which the DRAM might consume too much current and not work right (a quirk of those older DRAM chips). Fortunately this process does not care for the state of the address lines, in effect it will try to do a refresh but if it is not used who cares. It is a bit difficult to find a good datasheet for those old chips but there is a maximum period for RAS, which is a lot longer than a normal access (some milliseconds) so a fake RAS should be generated at a slower rate to disable the DRAM but keep it happy and consuming relatively low current.

[lliont]

And it is a bit more complicated, don't forget that ula in this bus has to check for the dsmc suddenly going high again by an expansion card and abort it's operation. So it can not function arbitrary fast or it will not give the card access.
If it controlled all the ram and not the 128K it could ignore the dsmc for the ram range.

The ULA does not check for this and really can't, if it sees it low by a certain half clock of the CPU, it will start the DRAM access if possible. The best you can do is prevent CAS from being generated if it is not low after that to prevent RAM corruption.

So it checks, you mean it can't check at the first cycle it sees the dsmc go low. As I implement it and it works with all the cards I have to test with, It starts the cycle by taking RAS low after dsmc goes low and it checks in the next half cycles if it then turns high and aborts the operation by taking RAS high again and does not generate the cas, that is what "it checks" meant in that context.

[lliont]

Fortunately the mux select and output enable lines are separate from RAS and CAS, as well as the DRAM WE. That being said you must not completely stop toggling RAS because it is used for the internal charge pump to negatively bias the substrate of the DRAM chips, without which the DRAM might consume too much current and not work right (a quirk of those older DRAM chips). Fortunately this process does not care for the state of the address lines, in effect it will try to do a refresh but if it is not used who cares. It is a bit difficult to find a good datasheet for those old chips but there is a maximum period for RAS, which is a lot longer than a normal access (some milliseconds) so a fake RAS should be generated at a slower rate to disable the DRAM but keep it happy and consuming relatively low current.

That is very helpful info for a future project to have in mind, thanks

[Peter]

That being said you must not completely stop toggling RAS because it is used for the internal charge pump to negatively bias the substrate of the DRAM chips, without which the DRAM might consume too much current and not work right (a quirk of those older DRAM chips).

Yes I forgot we discussed this half a decade ago here: viewtopic.php?p=24591#p24591
By experiment, I would still guess that this is not an issue for constantly deselected chips.

[Nasta]

That being said you must not completely stop toggling RAS because it is used for the internal charge pump to negatively bias the substrate of the DRAM chips, without which the DRAM might consume too much current and not work right (a quirk of those older DRAM chips).

Yes I forgot we discussed this half a decade ago here: viewtopic.php?p=24591#p24591
By experiment, I would still guess that this is not an issue for constantly deselected chips.

With no RAS othing will break because it is a matter of internal power sequencing and the chip has to work safely until it is internally set up. Mostly the only clue in the data sheet is that a number of RAS cycles are needed before the chip actually responds as stated in the datasheet. The difference is that the power consumption might be higher than necessary but then it also increases proportional to the RAS frequency so there are options
Needless to say but here I will say it anyway, there are variations between chips of various manufacturers and of course no specs for this.