This is a snapshot of the ROM port area. The top J2' area is the ROM port holes. The lower block is a duplicate. It has extra holes to the left, that will make a 2x20 block in the next revision. Those extra 10 pins add A16..19, R/W, CLKCPU, and some bus signals to be decided, so full expansions can be installed internally. I might add a few more pins so ALL address lines can be accessed.
This opens up a whole separate discussion, so I am going to start a separate discussion. Because that's where separate discussions belong
