The Sinclair QL Forum

I have been trying to contact Leon, the designer, about the QL 8301 CPLD Compact unit but he hasn't responded. Looking at when he was last logged in, it appears that it was last year so some time ago.

Would someone knowledgable be able to advise please?

1. Using the current Quartus-web-13.0.1.232-windows software, it often complains that the JTAG ID is different from the .po file and refuses to program the CPLD but the chip is Altera EPM7160STC100 as specified. However, after messing with the config somehow, it would finally program it. But since I didn't know exactly how to get it to program, I had to go through that each time with (to me) random changes to make it to program. I note that ​the .po file contains the string EPM7160STC100-10. I couldn't hex edit it as it has a checksum on the file and Quartus would complain and refused to load. What is the correct steps to program it without try and error please?

2. The CPLD gets rather hot after a while. In fact, it was hot enough that if the QL is rebooted by pressing the reset button, it would often display a green screen after the multi-colour initial screen. Once the chip cools down, it is back to normal though. I read from one of the forums where you were discussing about the project that by switching a parameter on the Quartus programming software from auto to off, it doesn't get hot any more. What is that parameter and where is it in the Quartus software please as I couldn't find it?

I would be grateful for advice please. Thanks.

Regards,

Li

Hi,
Interested about it too.

I want to do a openhardware version of the board.
But if you are experiencing such banch of problems, that discorage me to even start to do it.

Just... Lliont is answering and written about his project, but this thread (IMO) is in the wrong place. General chat?

It should be in Hardware.

LBS wrote: Sun Nov 10, 2024 10:51 am Looking at when he was last logged in, it appears that it was last year so some time ago.

Leon literally replied to a thread today and has been pretty constantly on this forum throughout 2024, so I'm not sure where you had been looking.

Hi,

Have you all tried to look at the project page?

https://hackaday.io/project/197484-lion ... inclair-ql

Hi
I confirm that the CPLD gets very hot, but I am using it for more than a year in my QL and haven't seen any problem. Actually I am using it right now in the QL I use for development that is powered all the day and half the night and I reset many times.

Are you sure that it is well soldered and the problem is not a pin that looses contact when it gets hot?

The parameter has to do with building the pof file but unfortunately with this parameter to off other problems occur.

I'm very busy with the other projects but one day I will port it to another CPLD maybe 3.3V that will run cooler.

How did you tried to contact me because I didn't received any message from you.

regards
Leon

Also the contact with the socket could be the problem, I hope you used the thin pins I describe in the web page, I don't believe it has to do with the temperature of the chip itself.

You could also try a flat IC heatsink with adhesive, there are some with just 1 mm height that will fit.

I have also made a version that uses the EPM7128STC100 but haven't build and tested yet.

Popopo wrote: Sat Nov 23, 2024 7:57 pm I want to do a openhardware version of the board.

As far as I know, the CPLD source is closed anyway.

Peter wrote: Sun Nov 24, 2024 12:29 pm

Popopo wrote: Sat Nov 23, 2024 7:57 pm I want to do a openhardware version of the board.

As far as I know, the CPLD source is closed anyway.

If I don't remember wrong, Lliont allows to modify the board and the bitstream is published.
If I am wrong, Lliont can clarify it, and I won't continue with this.

In any case:

Hardware design and Software released under the Creative Commons License BY-NC-SA

Yes both are published, the vhdl source code is not published, so anyone who wants can use the ula in a new board or design but he has to keep the same pinout for the cpld.

Well in this project, the VHDL source contains more than 90% of the hardware description, the rest relatively simple.
It is perfectly okay to keep it closed, but I would not call that "open hardware".