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QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 2:29 am
by ql_freak
On 68000/8 branches can only be +/-32K (16 bit).
I think I have heard since 020 branches can be 32 bit.
Is this true?
This would be great. But even if the 020+ (e.g. QPC2) supports it:
Does the MAC (CST MACro Assembler) support it (which was
developed for a QL with 68008)?
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 8:40 am
by tofro
ql_freak wrote: Mon Dec 18, 2023 2:29 am
On 68000/8 branches can only be +/-32K (16 bit).
I think I have heard since 020 branches can be 32 bit.
Is this true?
This would be great. But even if the 020+ (e.g. QPC2) supports it:
Does the MAC (CST MACro Assembler) support it (which was
developed for a QL with 68008)?
Yes, the '020 does support 32-bit wide PC-relative branches. (and, for example, 32-bit offsets for register-relative addressing as well). QMAC doesn't know that, though: it will assemble the instruction into a word-wide branch or offset, if possible, or spit out an error. GWASS will happily assemble such code into the proper instruction, however.
Whether it makes sense to have programs on the QL than will only run on certain machines, however, is another question.
I think it is better to jump through a register if you need such long relative jumps - That works on any machine.
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 9:01 am
by Derek_Stewart
Hi,
QMAC, GST MAC does not support 68020 opcodes directly, you will have to define a macro with the 020 op code definitions in a data statement.
But GWASS supports 68020,040,060
Which has same functionality and maybe be more up to date.
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 9:07 am
by tofro
Derek_Stewart wrote: Mon Dec 18, 2023 9:01 am
Hi,
QMAC, GST MAC does not support 68020 opcodes directly, you will have to define a macro with the 020 op code definitions in a data statement.
But GWASS supports 68020,040,060
Which has same functionality and maybe be more up to date.
Well, GWASS simply has other quirks. It doesn't consider displacements as relocatable, for example. If it isn't for a machine-specific driver, for example, that only has to work on one specific machine that you know has a 020+, I would really refrain from using such instructions.
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 9:09 am
by Derek_Stewart
tofro wrote: Mon Dec 18, 2023 9:07 am
Derek_Stewart wrote: Mon Dec 18, 2023 9:01 am
Hi,
QMAC, GST MAC does not support 68020 opcodes directly, you will have to define a macro with the 020 op code definitions in a data statement.
But GWASS supports 68020,040,060
Which has same functionality and maybe be more up to date.
Well, GWASS simply has other quirks. It doesn't consider displacements as relocatable, for example. If it isn't for a machine-specific driver, for example, that only has to work on one specific machine that you know has a 020+, I would really refrain from using such instructions.
I am confused by that statement, what use is using a 68020 assembley language programme on a machine that does not have a 68020 CPU.
OK, how do I get QMAC to assemble 68020, 68040, 68060 op codes, required on the Q40, Q60
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 9:20 am
by tofro
For very long PC-relative "branches" I have the following Macros for QMAC:
Code: Select all
* This macro jumps (in a "PC-relative" way) to a
* subroutine which would normally be not reachable
* by a bsr. Use in large programs you dont want to
* make 'impure'.
FARJSR MACRO target,register
EXPAND
lea .lab[.L],[register]
add.l ([register]),[register]
jsr ([register])
bra.s .across[.L]
.lab[.L] dc.l [target]-*
.across[.L]
ENDM
* This macro jumps (in a "PC-relative" way) to an
* address which would normally be not reachable
* by a bsr. Use in large programs you don't want
* to make 'impure'.
FARJMP MACRO target,register
lea .lab[.L],[register]
add.l ([register]),[register]
jmp.l ([register])
.lab[.L] dc.l [target]-*
ENDM
* This macro loads an address register in a "PC-relative"
* way with an address value that would normally be
* unreachable for PC-relative addressing. Use in
* large programs you don't want to make 'impure'
FARREF MACRO target,register
lea .lab[.L],[register]
add.l ([register]),[register]
bra.s .across[.L]
.lab[.L] dc.l [target]-*
.across[.L]
ENDM
Those macros work on any CPU and are simply used with a far-away label and an address register, like in
And do pretty much the same as the 68020 instructions (smash the address register in the process, however).
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 1:14 pm
by pjw
Perhaps I misunderstood, but to use Qmac to generate MC68020 code for an MC68020+ CPU you can "simply" add the binary inline. For example, the binary for BRA is %01100000 ($60) in the msb. If the lsb of the word is 0, then the following word contains the twos compliment displacement to the location you wish to jump to. For a 32 bit displacement the lsb must be $FF:
Code: Select all
* Test long branch
*
section test
start
nop
dc.b $60,$ff 32bit bra
here dc.l label-here
*
* Code to skip > 32k
ds.b 40000
*
label
moveq #-21,d0
rts
end
Simply assemble in Qmac, then load and call this code (QPC2 or Qx0 only!) It should return with the error Invalid syntax if it worked. The call code could look like this:
Code: Select all
100 CLCHP
110 ad = ALCHP(40100)
120 LBYTES 'win4_tst_BSRL_bin', ad
130 a$ = HEX$(ad, 32)
140 PRINT a$
150 HOT_STUFF a$
160 REMark JMON -1
170 CALL ad
180 RECHP ad
You could, of course make a macro to do that..
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 1:34 pm
by tofro
pjw wrote: Mon Dec 18, 2023 1:14 pm
(QPC2 or Qx0 only!)
That's exactly the point why I made this alternate proposal. My code runs everywhere.
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 1:45 pm
by pjw
tofro wrote: Mon Dec 18, 2023 1:34 pm
pjw wrote: Mon Dec 18, 2023 1:14 pm
(QPC2 or Qx0 only!)
That's exactly the point why I made this alternate proposal. My code runs everywhere.
I know, but my reply was more directed to the question asked by Derek: "OK, how do I get QMAC to assemble 68020, 68040, 68060 op codes, required on the Q40, Q60"
Re: QUESTION: Branch Size on QPC2 (68020+)?
Posted: Mon Dec 18, 2023 2:04 pm
by tofro
pjw wrote: Mon Dec 18, 2023 1:45 pm
tofro wrote: Mon Dec 18, 2023 1:34 pm
pjw wrote: Mon Dec 18, 2023 1:14 pm
(QPC2 or Qx0 only!)
That's exactly the point why I made this alternate proposal. My code runs everywhere.
I know, but my reply was more directed to the question asked by Derek: "OK, how do I get QMAC to assemble 68020, 68040, 68060 op codes, required on the Q40, Q60"
Ah, OK. My answer to that would then be "Don't".
