The Sinclair QL Forum

Hi,

can anyone confirm that a byte-wide read access to an even address with the Gold Card leads to two QL bus accesses, first the (intended) read access to the even address, then an (unintended) one to the following odd address? This is what I seem to see on the QL bus when I do a PRINT PEEK(even address).

Although my suspicion is nurtured by the fact that Stuart Honeball had to implement his own hardware to split the 68000's 16 bit accesses into two 8 Bit accesses, I would not really expect such a sloppy implementation. According to the 68000 docs, only one of UDS / LDS is activated on 8 bit read, so a correct implementation is possible. Maybe I'm wrong and it is a different issue, IIRC the Gold Card sometimes provides insufficient hold time on the address bus.

Super Gold Card works correctly, because the CPU itself implements 8 bit accesses. 68008 also works correctly of course.

Peter

Update: It appears to be a consequence of the Gold Card already changing the address bus while ROMOE is still active. Effectively splitting the bus access into two. A long one and a short one. Slow logic does not see it, fast logic does...

One more update: I see on the scope that Gold Card address bus starts changing 37 ns before ROMOE is fully de-asserted. I did not remember the GC hardware was that buggy.

Unfortunately I don't have a GC, but I do remember there were several revisions of the INGOT for the GC, maybe that's the reason?

Yes, that could be, but mine is a red Gold Card and the PLD is labelled "INGOT20". So I think it is not an early version.

Wasn't ingot21 the last release of that?