Q_Liberator malaise

[Derek_Stewart]

Hi

The QXL has a 68EC040 40/50 Mhz CPU but the 68040 halfves the clock speed to 20/25 Mhz, runs the same version of version of SMSQ/E.

I never had many problems relating to Qliberator compiled files or SBASIC files.

Is there a difference in the QXL and Qx0 code ?

[Peter]

Is there a difference in the QXL and Qx0 code ?

The QXL runs writethrough only. Maybe the cache mode tool from Mark works there. If it does, you could try to activate copyback and see what happens.

[Peter]

Is there a difference in the QXL and Qx0 code ?

The QXL runs writethrough only. Maybe the cache mode tool from Mark works there. If it does, you could try to activate copyback and see what happens.

It would be interesting if you actually try and post the outcome here.
The tool is here: https://dilwyn.theqlforum.com/qx0/cachemodes.zip

[Peter]

And for completeness, here is the patch that was applied to SMSQ/E 2.98:

Code: Select all

10 a=ALCHP(FLEN(\smsq_rom))
20 LBYTES smsq_rom,a
30 IF PEEK_W(a+1300)<>20091 : GO TO 110
60 IF PEEK_W(a+1306)<>0 : GO TO 110
70 IF PEEK_W(a+1308)<>49152 AND PEEK_W(a+1308)<>-16384: GO TO 110
80 POKE_W 1304+a,8252
90 SBYTES smsq298_patched,a,FLEN(\smsq_rom)
100 STOP
110 PRINT "wrong or already patched rom"
120 STOP
130 DEFine PROCedure sa: SAVE_O win2_patch:END DEFine

[Derek_Stewart]

Hi Peter

I remember being given SMSQ/E 2.98p to programme into 2 Eproms for Q60 boards.

I did wonder what the patch did, here was an item QL Today about the patch. I will find out the issue details

Tony Tebby handed over the SMSQ/E source to the SMSQ/E committee, or Cabal as it came to known. Then major development started in v3.00 with removing the Slave Blocks.

I did wonder if as SMSQ/E was updated, whether the patch code was included.

I will start studying the SMSQ/E source and work out what the patch actually does.

When collated the SMSQ/E Reference Manual, it was clear the updates for SMSQ/E were not done very well and update information seemed to scattered all about.

There seems to no consultation process of updates to the SMSQ/E code. Just an observation not a complaint.

There is slot of information in the Reference Manual regarding 68040 and 68060 CPUs, so maybe there is a start in the resolution.

Mark Swift's Cache Mode software is very well documented with comments in the source code.

So lots of information just need to understand it.

[Peter]

Mark Swift's Cache Mode software is very well documented with comments in the source code.

Yes, but for QXL you'd probably need the separate tool to activate copyback.
I doubt that the QXL can be used in copyback mode at all due to the emulation requirements, but you might try and inform us.

[Derek_Stewart]

... in QL Today vol 7 issue 4, the famous Tony Tebby article "Pirates and Mad Sheep", on page 25, Tony Tebby gives details of a bug in the Q40 hardware initialisation routine, maybe this a clue to what is going on.

[pjw]

... in QL Today vol 7 issue 4, the famous Tony Tebby article "Pirates and Mad Sheep", on page 25, Tony Tebby gives details of a bug in the Q40 hardware initialisation routine, maybe this a clue to what is going on.

Thanks for the reminder, Derek. Nice read too, although its a sad story.

I dont know anything about caches, CPUs, etc at this level, but it is obvious that there have been problems along the way, and that the matter might be worth looking into. I guess very few among us now would know where to look for something like one wrong bit in 1k of dense code!

Puts me in mind of a story about a gentleman who saw an old lady rummaging around outside, obviously looking for something - her needle. The kind gentleman offered to help her looking, and so they scrabbled around on her lawn, carefully searching every square inch. After many hours of this the gentleman asked "Are you sure you lost it here?", "Oh no," said she, "I lost it inside, but its too dark to go looking there!"

I dont know where is the best place to start, but I dont feel like spending hours looking in the wrong place.

[tofro]

I dont know where is the best place to start, but I dont feel like spending hours looking in the wrong place.

Well, likely its this

Code: Select all

	
	dtt1	#$00ffe020		; set DTT1 for all cached copyback
;	dtt1	#$00ffe000		; set DTT1 for all cached write through

in hw_init_asm

(See the 1 bit diff? )

[pjw]

<>
(See the 1 bit diff? )

I do indeed. But are you saying this is the problem, or that this was the problem?