Re: Sinclair QL Floppy Disk Interfaces
Posted: Mon Oct 21, 2013 4:42 pm
This was about a Super Gold Card remake:
Secondly, you don't just need functional sourcecode, you need a timing model. Ancient development tools had poor support for that, so you'd have to read through databooks from decades ago and manually calculate timings.
Thirdly, modern chips won't let you implement the minimum asynchronous delays of ancient chips, simply because they are way too fast. You'd have to work around that, which can be challenging.
Fourthly, modern chips achieve nanoseconds timings, so they can be affected by high frequency faults on signals, which had no visible effect while chips were still slow enough to ignore them. So you can have logic and timings correct, but fail, because you have to interface to an old generation design with meagre signal quality. This is also a problem with QL-SD by the way.
Fifthly, modern FPGA won't have 5V tolerant IO. You'd need level shifter chips surrounding your FPGA.
Sixthly, modern FPGA are a pain for manual soldering. In the best case, you have no BGA, but a 0.5mm pitch TQFP with lots of pins. This hinders building the very low quantities for QL, which are no comparison to the Spectrum by the way.
Seventhly, even to deal with all the bugs and problems of FPGA development software in a modern design is a challenge (once you leave the path of well prepared demos for evaluation boards and start your specific design for your specific PCB).
Eighthly, all of the above applies to logic you still understand to some degree, because you once wrote it yourself. Porting a complex ancient logic written by someone else can be more time consuming than writing it from scratch.
Ninthly, the one who writes this has successfully designed complex mainboards and graphics chips. You can not expect similar knowledge from a trader, or persons he could easily hire for a design.
I still wait for one of those who find chip design for the QL easy, to actually do it themselves and prove.
Firstly, complex ancient logic code can be hard to port to newer development tools. I remember my massive problems even to port my Q60 logic to the next generation development tool. In the end I gave up, and still use the ancient tool (which won't work under a modern Windows, not even in a virtual machine).skagon wrote: You can always get a newer model and just port the logic code to the newer chip. On the VHDL level, it's a day's work tops and Altera will have guides (if not porting tools too) to tell you how.
Secondly, you don't just need functional sourcecode, you need a timing model. Ancient development tools had poor support for that, so you'd have to read through databooks from decades ago and manually calculate timings.
Thirdly, modern chips won't let you implement the minimum asynchronous delays of ancient chips, simply because they are way too fast. You'd have to work around that, which can be challenging.
Fourthly, modern chips achieve nanoseconds timings, so they can be affected by high frequency faults on signals, which had no visible effect while chips were still slow enough to ignore them. So you can have logic and timings correct, but fail, because you have to interface to an old generation design with meagre signal quality. This is also a problem with QL-SD by the way.
Fifthly, modern FPGA won't have 5V tolerant IO. You'd need level shifter chips surrounding your FPGA.
Sixthly, modern FPGA are a pain for manual soldering. In the best case, you have no BGA, but a 0.5mm pitch TQFP with lots of pins. This hinders building the very low quantities for QL, which are no comparison to the Spectrum by the way.
Seventhly, even to deal with all the bugs and problems of FPGA development software in a modern design is a challenge (once you leave the path of well prepared demos for evaluation boards and start your specific design for your specific PCB).
Eighthly, all of the above applies to logic you still understand to some degree, because you once wrote it yourself. Porting a complex ancient logic written by someone else can be more time consuming than writing it from scratch.
Ninthly, the one who writes this has successfully designed complex mainboards and graphics chips. You can not expect similar knowledge from a trader, or persons he could easily hire for a design.
I still wait for one of those who find chip design for the QL easy, to actually do it themselves and prove.