The Sinclair QL Forum

Dave wrote: Wed Jan 08, 2025 6:58 pmIt would be quite simple to use a spare PIO to define a SRAM chip-style interface.

As for implementing Q68 graphics that way: I'll believe it when I see it.

Such interface means at least: Two data strobes, R/W, chip select, 16 data lines, 21 address lines for the VRAM area itself - and to make actual sense, it would require even more lines, so no external logic chip is required for decoding. Not enough pins free for that, even if internal memory was large enough. Mind you: As soon as an extra programmable logic chip is required, one can use a low-end FPGA, which does whole video task, and the cost saving idea by using a µC becomes pointless.

I think the target was something like a SGC, like it was for the original Aurora. In that case the bandwidth is far lower, not evenb 2Mbytes/sev as it emulates the original 68008, and needs in theory up to 256k of screen RAM, but these days not nearlčy all Aurora resolutions make sense, so 192k is enough, especially as the allocation of that RAM can be much more optimal because for Aurora, the bitmaps were always the same, the difference was how much of it was visible. So, it was 1024x1024 in 4 colors, 1024x512 in 16 colors, and 512x512 in 256 colors. These days, up to 1024x768 in 4 and 512x284 (based on 1024x768 monitor timing) in 256 colors is fine, needing 192k. 640x480 in 16 colors (although 16 colors was never a QL thing, we could use 8 as a template) needs 150k.