The Sinclair QL Forum

techfury wrote: Thu Mar 20, 2025 12:35 am I have not actually tried a 1772, but I don't know why it wouldn't work, the only difference between 1770/1772 is the step rate/settle time tables, and the TC firmware is set up to work with either. I think the PCB is even marked "WD1770/1772"...

And yes, GAL16V8B or ATF16V8B will work equally fine. Not sure what the needed minimum speed is, but empirically, 15ns ATF and 20ns Lattice GAL worked fine for me.

I have redrawn the board a bit. My OCD kicked in a bit when I saw the RAM and ROM at a 14 degree angle
But I used the same schematic so fingers crossed...

And I ordered a WD1772 replacement from vRetro. I believe that one is based on an FPGA. It would be nice if that one is working too. The WD1772s are getting harder to source, so a modern replacement would be very welcome.

Anyway, back to the soldering station... I'll report back when I have not blown up my QL...

Moment of truth...!
It fits alright!


The only thing that bothers me is the green buck converter. Probably going to replace it with a black Traco or similar version.


And yes!!! It is working! No magic smoke... QL reports 896K of RAM and both floppy drives are working.


@techfury, I can confirm that the WD1772-PH 00-02 version works. I hope to receive the vRetro version of the WD1772 and test that one. Would be nice if it did as that would mean that it can be built with readily available components. Haven't check the current draw yet, but everything is cool to the touch, except for the WD1772 and the 16V8 that get slightly warm. But that was to be expected I guess.

Thanks to techfury, Alvaro and Tetroid for the work they already did.

Time for a beer now here in the NL. Going to enjoy the sunny weather while it lasts...

BTW, is there a schematic diagram? Didn't see one in the github project...

Nasta wrote: Sat Apr 05, 2025 7:33 pm BTW, is there a schematic diagram? Didn't see one in the github project...

There is a schematic on techfury's Github. It is not in PDF format, so Kicad needs to be installed.
Made a PDF that is attached below. My schematic is basically the same. Just the layout is different.

Cheers!

Using an 8 MHz clock oscillator saves one IC, two resistors and some space on the board...
It should be possible to also remove 4 diodes and make the whole thing faster with a few changes to the GAL programming, will look at the source...

Nasta wrote: Mon Apr 07, 2025 12:04 pm Using an 8 MHz clock oscillator saves one IC, two resistors and some space on the board...
It should be possible to also remove 4 diodes and make the whole thing faster with a few changes to the GAL programming, will look at the source...

Oh, that would be great. I can imagine the ATF16V8 could generate a dedicated DTACKL pin which is only driven low when needed and tri-stated when inactive.
Sort of a make-shift open drain pin. Is that what you had in mind? That would indeed allow for the removal of a few diodes.

I would appreciate if you could look at the code. It's been a while since I used CUPL or ABEL. Probably a few decades ago

Yes, one on should be able to implement DTACK.
Also there are two 74HC04 in there, one of which has 2 unused inverters, and the other has 3.
The one with 3, uses 2 for the floppy WD1772 clock and one to invert the RDWL signal for the ROM. If an integrated 8MHz oscillator is used, two of those inverters are not needed, and the one on the ROM is not necessary as the function can be integrated into the GAL.
I suspect the reason this was not done is because the original PALs are not as versatile as the GALs are so now some more logic can be squeezed in.
Also, since there is actually 1M of SRAM on board, half of one chip (256k) is not used. There is an opportunity here. The internal QL RAM is quite slow because it is also accessed by the video ULA. The nice thing about the way the QL decodes it's internal parts is that this can be externally disabled and then the internal hardware replaced by hardware on the expansion bus.
In this case, the top 64k of the internal 128k can be replaced by part of the unused chip directly, because even though the video ULA controls it as if it can be used for video RAM, it can't be used for that purpose.
As for the bottom 64k, these are used for the two screen areas. However, the video ULA only reads the RAM to generate the video. This makes it possible to 'shadow' it by external RAM. This is done by letting the on-board RAM behave as usual, including the slowdown, when data is written, but it is already written into the same address into the RAM chip on the 'trump' card. This insures that video data is copied to both RAMs at the same address. This way, the video ULA can read it slow from the QL motherboard RAM, and the CPU can read it at full speed from the 'trump' card chip. The hardware is already set up so this can even occur at the same time.
This actually makes thus equipped QLs a bit faster than the original trump card expansion (or indeed any other classic RAM expansion) because a lot of data in the motherboard 128k is used for system data structures that are accessed very often, along with video RAM. The latter benefits quite a lot since most of the time for pixels to be drawn on the screen, the appropriate bytes have to first be read from the screen RAM, the modified internally inside the CPU, then written back, and often repeatedly in a tight loop. Having the read portion be more than twice as fast than writing has a nice positive effect.
The logic to decode and implement this should fit into the existing GAL.