Re: schematics for floppy disk interfaces
Posted: Fri Oct 02, 2020 10:07 am
Some further uncovered info on the CST Q Disk from the pictures :
1) Under the cover of the Q Disc that has not visible heatsink is the regulator and heatsink - not sure which is the earlier model, but one has heatsink and reg on the side and one is under the plastic cover (on that one - there is nothing else except the disk drive connector)
2) Chips for the one in the picture 74LS240 - Octal 3 state buffer, 74LS124 Hex D type Flip Flop, 74Ls04 Quad NAND (with 8MHz xtal), 74LS03 Quad NAND OC, 74LS10 Triple 3 input NAND, 74LS2x6 (I could not see if this was an 8 or 6) Quad XNOR.
3) The Quad XNOR will decode the SP0-3 and A14-!7 address lines - when they are equal the interface is select (default as described in my last post) - the small transistor in the circuit will signal DMSC to disable the internal circuitry in the QL allowing this interface to take over - in conjunction with logic in 8) below
4) The 74LS04 chip and crystal provide the 8MHz clock to the disk interface chip (WD1770)
5) The 74LS240 chip buffers the disk interface signals to the connector and outside world
6) The 74LS174 probably provides the additional I/O port for drive number select
7) The ROM is only an 8K version - so the ROM / I/O split may be done simply using A13 line to select either the ROM or the I/O on the card
8) The other logic chips no doubt used to decode R/W, A18, A19, DS and provide DTACK back to the QL
1) Under the cover of the Q Disc that has not visible heatsink is the regulator and heatsink - not sure which is the earlier model, but one has heatsink and reg on the side and one is under the plastic cover (on that one - there is nothing else except the disk drive connector)
2) Chips for the one in the picture 74LS240 - Octal 3 state buffer, 74LS124 Hex D type Flip Flop, 74Ls04 Quad NAND (with 8MHz xtal), 74LS03 Quad NAND OC, 74LS10 Triple 3 input NAND, 74LS2x6 (I could not see if this was an 8 or 6) Quad XNOR.
3) The Quad XNOR will decode the SP0-3 and A14-!7 address lines - when they are equal the interface is select (default as described in my last post) - the small transistor in the circuit will signal DMSC to disable the internal circuitry in the QL allowing this interface to take over - in conjunction with logic in 8) below
4) The 74LS04 chip and crystal provide the 8MHz clock to the disk interface chip (WD1770)
5) The 74LS240 chip buffers the disk interface signals to the connector and outside world
6) The 74LS174 probably provides the additional I/O port for drive number select
7) The ROM is only an 8K version - so the ROM / I/O split may be done simply using A13 line to select either the ROM or the I/O on the card
8) The other logic chips no doubt used to decode R/W, A18, A19, DS and provide DTACK back to the QL