My current QL accelerator project

[Pr0f]

Looking at your state machine logic - you sample VPA in state 4 - but it seems to be implied that this is for VMA access (6800 series Synchronous access).

The VPA signal has 2 purposes on the 68000/68008 - it is either used for the above purpose - or to respond to an interrupt acknowledge cycle from the CPU to perform the autovector routine for the interrupt level - which is how it is used in the standard QL.

Interrupt ackowledge cycle is signified by FC0, FC1 and FC2 all being 1, and the QL - in typical cost cutting Sinclair style only uses FC0 and FC1 to feed into a NAND gate and create the VPA response. Since no other interrupt levels were really designed into the QL - it is assumed any interrupt is a level 2 Interrupt (IPL1 low), so this mechanism whilst very limited works well on the QL. The interrupt service routine will then query the ZX8302 to find out who's asking for attention.

Watching the video - it's clear that F2 is effectively being detected by the OS - probably some semi random chance thing, but you can see the classic blue screen followed by the red one immediately afterwards in the booting video - then the random 'key presses' - which I presume are the result of the interrupt routine just doing it's own thing.

I couldn't see in your emulation files where these Function code outputs are set - I probably need to study it a bit longer.

You may find this post useful - as a few folks contributed to get a better understandting of what the ZX8302 does and the fact the registers are not symetrical around read and write - I.e. 18020 address in read is IPC status and other status, but in write is for Microdrive control. 18003 is the register for writing to IPC.

viewtopic.php?p=25112&hilit=zx8302#p25112

The link between the IPC and the ZX8302 is a little weird - as the IPC uses it's /WR line to signal acknowledgement of the data bit (COMCTL) and the data itself is driven or read by either side on COMDATA - which is a Port 2 line on the IPC chip, and open drain on the ZX8302 I believe. The IPC chip has week pullups internally.

It's suprisingly easy to upset this communication if it gets out of step, which is I suspect what's happening in your example.

[Will James]

Hi Pr0f, sorry for my quick reply but I'm at a festival where internet is very intermittent. The Amiga Pistorm doesn't emulated function codes or interrupt acknowledge cycle so VPA never gets asserted by the QL hardware. The Mashushi emulator assumes auto vector interrupts and the are set in the execution loop when ipl_Zero goes low. Also neither unexpanded Amiga or QL uses the 6800 peripheral cycle so again VPA never gets asserted. I can't think of a reason this would cause problems with the IPC communication, but that doesn't mean there isn't something.

The Zx8302 thread looks very interesting I will try and get ready up on it over the next couple of days...

All the best, Will

[Pr0f]

Hi Will,

I suspect from when IPL is asserted on your pistorm to when you process the read to the IPC is probably a lot shorter than the sequence on a real QL - so it may then be some sort of timing issue. Generally I think the IPC is just polled by the ZX8302 as part of the 50Hz (regular frame interrupt) that the ZX8301 video ULA is pushing at the ZX8302 on vsynch.