Dave wrote: Tue Dec 31, 2024 7:37 pm
Peter wrote: Fri Oct 11, 2024 1:00 pm
The first 16550 version with working FIFO came in 1987.
I have tubes of later 16550-compatible ICs. I have never seen a QL driver to support them though - just the older and less useful 6850 that has an incompatible register structure.
The problem with even the original 16450 descendants like the 16550 with a working FIFO is that there still was no hardware handshake.
The FIFO would in a roundabout way solve this problem for receive but it is completely useless for transmit.
The 16550 is based on the host being able to react sufficiently quickly to an interrupt it generates when data is received, to either transfer the data from the chip to the host, or if some buffer is full, set the appropriate handshake lines in software, basically like writing new states to output pins.
When the FIFO is present, it buffers received data in hopes the host will be able to react before the FIFO becomes full and set handshake lines to prevent the transmitter sending the data so the FIFO will not overflow. With a big enough FIFO it can _almost_ be guaranteed (one could argue that if the host does not react to the interrupt then something is badly wrong so lost serial port data will be the least of the problem).
That being said, the transmit FIFO is basically useless because this time the host has to keep checking the handshake lines to see if it is even permitted to send the data, so not much use for it sitting in FIFO. The transmit FIFO can only be useful if one can guarantee there is another larger receive FIFO at the other end, but there is still no guarantee a situation will not arise for data loss to occur.
All that being said - FORTUNATELY the newest chips (with multiple channels and even larger FIFOs) have implemented hardware handshake, which actually makes the FIFOs very useful. In fact the implementation is clever enough to handle various edge cases, like what happens if the receiver receives bytes but the FIFO never fills to the point where an interrupt to the host is generated - after a timeout, an interrupt is still generated to have the host clear out the FIFO, as the bytes received may well be all the remaining bytes to be received in the first place.
Some of these chips also can use quite high baud rates (like 3Mbaud) which is useful if one wants to make a QL to PC comms bridge using an USB to serial adapter on the PC side, or communicate with an ESP32 module really fast.
