Connecting a uC (PIC) to the QL

[fuasn]

Hi,
I would need some advice regarding connecting a uC (PIC18F56Q83) to the expansion port, maybe someone here has experience with that.

I have made a PCB with a CPLD (ATF1502 for addressing, DSL, DSMCL, DACKL, the SP lines) and a PIC together with some other chips like the databus is decoupled with a 74LS245. The QL is connected to a small adapterboard that allows me to connect to the PIC PCB with a ribbon cable (easier prototyping as the connectors are quite expensive). The ribbon-cable is actually quite long (50cm).

So my problem currently: As soon as i solder in the PIC, the QL doesnt start, but gives a picture on startup that looks a bit like if it would be a memory error. When i remove that PIC from my PCB, everything works again, even with the PCB connected via that ribbon cable. I couldn't find any shorts on the PIC legs.

The PIC currently only has A0-A13 directly connected to the QL. I previously had RDWL, DTACKL, EXTINL, IPL0L, IPL1L directly connected, but in trying to fix my problem i removed these connections (actually the PICs legs...), didnt help. The address lines are all set to INPUT on the PIC. Could it be that the PIC is drawing too much power from these address lines and i also need to decouple them ? The address lines are also connected to the 1502 and that doesnt seem to make issues (the 1502 doesnt run anything yet however).

Or could that maybe be some problem with the uC messing up the address lines during startup ? Any other idea ?

best & thx in advance
manfred

[ones' complement]

Surprised the QL still worked with address lines extended 50cm even without PIC connected, I would have at least used buffers.

BTW I bought these DIN41612 female R/A connectors a while ago and they were OK:
https://www.aliexpress.com/item/32808141634.html

[fuasn]

thx for you reply.

wow, that says €6 per 5 pieces. i order them for ~7€ / piece ...

nevertheless, redesigning to use buffers / transceivers for data + address lines. i'm not very sure if that is really coming from that 50cm cable, i had the same problem also with a previous version of the PCB that was directly connected to the expansion port. Interestingly, no issue with an SRAM (that of course was also connected to the databus and addressbus) there, but that SRAM was disabled by a GAL on this board by default.
as said, will try with transceivers ( 74LS245 ) that are pulled up so OE is disabled by default and only enable them when the CPLD detects that i'm addressed.

[Pr0f]

Where do we start?

Are you connecting a pic pin directly to the QL address bus? If so - what settings have you enabled on the PIC pin besides telling the PIC it's an input? Did you disable any possible analog function on those pins? What about week pull down / pull up?

What's your application? What will the PIC be doing?

[fuasn]

Thx for your questions Pr0f,

The QLs address bus is directly connected to the PIC (well, A0-A13). The CPLD has A14-A19 (also directly, didn't make an issue so far).

The PinManager UI gives me the following options, thats what i selected for these A0-A13:
Analog: not selected
Start High: not selected
Weak Pullup: not selected
Open Drain: not selected
Slew Rate: is selected (default)
Input Buffer (ST / TTL): ST

The databus already has a transceiver between but i didn't think that the addressbus could also need one.
The application would be basically send/receive data from QL to PIC (and the other way round) and the PIC then forwarding it to SPI and/or UART. Based on that maybe more then.
And the optional SRAM would simply be a ram-extension (if already have a pcb on the expansion bus containing a CPLD, that shouldn't be too hard then)

[Pr0f]

Do you need so many address lines for the PIC?

Are you using it as memory from the point of view of the QL accessing it?

[fuasn]

Yes, the PIC would be "memory mapped" from the QLs point of view, driver, 1 or 2 status bytes, the rest rx/tx buffer.
i think it could work out with less address lines, like just 8, having a max of 256 bytes as ringbuffer for rx/tx then. But that doesn't leave any space for the driver then, what i mean the thing starting with a $4AFB0001...

i could use an extra ROM for that driver, but if possible, i thought the PIC could simply provide it.
i currently try to redesign with 3 245's, one for the databus, 2 for A0-A13 and the CPLD has a pin to the PIC that tells him if its addressed & if its read/write (derived from RDWL) . some more connections from PIC <-> CPLD since some legs are free for future use.

[fuasn]

if someone is interested, i'm adding the schematic for the next (v6) design, would be glad for some feedback.

Schematic_QLPeripheral.pdf

(242.86 KiB) Downloaded 188 times

best & thx for replies so far
manfred

[M68008]

Careful with DSMCL, it should never be set to low (except by the CPU, through a resistor)

[fuasn]

thx for your input M68008, appreciate it

but the technical manual says:
"In peripheral cards which are to be added to the QL, it is necessary for each
card to disable the circuitry on the QL itself when that peripheral card
recognises its own address.This is achieved by pulling signal DSMCL high
before DSL goes low including buffering times."

that makes me think i need that DSMCL pin to indicate the 8031 that my PCB is responsible for that memory address that is on the adr-bus, or am i wrong with that ??