The Sinclair QL Forum

[...] Interrupt handling is expensive, on a 68k it's 44 cycles, which is roughly 2-3 instructions (not counting the handler and the rte, and this is for auto vector interrupts. When the device provides the vector, its even worse... you can't write even a do-nothing interrupt handler (other than ...

Can an interrupt be too frequent? Even in the fastest system?


Sure - when the overhead of just responding to an interrupt gets to be on the order of normal processing, you got a problem.
Of course there is one more way this can happen and that's when interrupt processing (i.e. actual code that ...

Interrupt (level 2) on the QL is slow as it calls the QDOS handlers.

Can't be avoided as the vecors are in ROM. On the other hand, there is not a lot of code between the interrupt and user code, if you take some care.


I think it also slows down the CPU while it's pending since it asserts the ...

Not sure what you mean with "take control back". The CPU is always in control. It can be made to wait until the video circuitry is done generating a frame (that's done by the 8301 by simply not generating a DS


That would be DTACKL, not DS. I know the author of the post knows it, just correcting ...

So technically speaking the 68008 is using aysnchronous access - requiring a device to respond on DTACK pin when it's ready to send or receive data, the DS pin from the CPU initiates the request. If your external hardware raises DSMCL when the address matches one you are providing an override for ...

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To be sure about the priorities for the system before to go ahead...
When the system turns on, the CPU try to read addr 0h (ROM), and all the other ICs (ULAs) keep how? "awaiting/sleeping" mode?
Could They try to call a CPU IRQ at any time even when the CPU didn't started?
I guess all they ...

One of the things I regret is that people have always misused the SP0..3 lines. Sinclair's intention was not communicated clearly so it was used poorly by even high status members of the hardware dev community.

The intention of S0..3 was to be tied to GND on the J1 connector, and each ...

OK, so (I know, hard to believe) I am going to try and keep this short.

8301 is the main decoder in the QL an decodes ROM, RAM and IO.
ROMOEH is a high active line from the 8301 to the ROM sockets and also appears on the expansion connector J1. It is a direct output, do NOT tie it to another output ...

So, a bit more on interrupts:

Again, some notes on how the 68k interrupt system works:
When a non-masked interrupt level is recognized on the ILP lines, the 68k will start exception processing (exceptions being a much wider category than interrupts, but in this case interrupts are what we are ...

Quick answer to the last 2 posts, this is true for reproducing audio samples. By the time PC plug and play came into the mainstream, practically all sound chips had some form of FIFO of the ADC and DAC, i.e. digital PCM audio data in or out.
MIDI is a 'bit' different, in that it can be used as an ...