The Sinclair QL Forum

Hi Pr0f, sorry for my quick reply but I'm at a festival where internet is very intermittent. The Amiga Pistorm doesn't emulated function codes or interrupt acknowledge cycle so VPA never gets asserted by the QL hardware. The Mashushi emulator assumes auto vector interrupts and the are set in the ...

Hi,

I have created a folder with a video of what QLPiStorm is doing during boot and the included the Logic Analyser trace file
in case any brainy bods out there fancy taking a look. It's all explained in the readme.txt file.
There are a few photos and the current Verilog and C files.

It's here ...

Pah! I've been desperately trying to get this working before I go off to Spain for the summer, but it looks like I'm going to have to come back to it in September... thanks to everyone who has helped me with top QL hardware information. This has been a lot harder than I first imagined, the IPC ...

Hi All

Does anyone know how the IPC detects that the Read register ($18020) has been read in order to put the next data bit on D7?
Also, is there a PALASM source file for IC38 HAL16L8 anywhere even if it's reverse engineered?

Cheers

Will

@Martyn - Ah, so your saying the QL doesn't use the M6800 Peripheral Interface for register but uses VPA and generates VMA for Interrupt cycles. I will have to check this is not confusing my state machine logic...

Cheers

Will

The plot thickens, I see that that IC24 IPC sends it interrupt to IC38 HAL16L8 mystery chip... which is also connected to !VPA so it could be using the 68000 slow peripheral timing for IO registers. I hadn't considered this 'till just now... with all my ROM and RAM tests I never witnessed !VPA in ...

Hi XorA

I'm doing this as the first line in my m68k_write_memory_8() and m68k_read_memory_8()

address = address & 0x03FFFF;

Do you think that would cause the problem?

Tried 0x0FFFFF instead but it still crashes...

Well Interrupts are now working how I expected.

IntsWorking.png

Which means reading and writing to the Interrupt register
is definitely working. The problem was just my lack of understanding of QL and Musashi interrupt handling worked.
I also worked out what all the black space is in the TXN ...

Peter, some good points there, I have heard people mentioning on here that modern fast logic chips can cause problems with timing etc.
with the QL. I've had a few ideas about what's going on with the interrupts which I'm going to implement now that I understand how the
interrupt register works using ...

Ha! That'll be why they keep a copy in the system variables for setting and clearing the register
in the JS ROM.
It all makes sense now.

L2B88 move.b sv_pcint(a6),d7 ;interrupt register setting
ori.b #pc.intrg,d7 ;clear gap interrupt
andi.b #$DF,d7 ;disable gap interrupts
move.b d7,pc_intr-pc ...