Hi Dilwyn
I sympathise :-) Something you've probably already explored, but thought to share...
Like most Routers, your EE SmartHub will be running an embedded Linux-variant and exposing any USB mass-storage via the SMB protocol. Typically, the version of the SMB protocol supported by these ...
Search found 1062 matches
- Thu May 15, 2025 2:21 pm
- Forum: The Off-Topic Section
- Topic: Win 11 networking
- Replies: 7
- Views: 137
- Sun May 11, 2025 12:34 pm
- Forum: General QL Chat
- Topic: Announcing RetCon 2025 - the Retro Computing festival!
- Replies: 0
- Views: 185
Announcing RetCon 2025 - the Retro Computing festival!
Good morning all and happy Sunday!
Just a short announcement that this year's RetCon event is taking place on Saturday May 31st in West London - details and ticket sales available via the links further below.
IMG_20250511_131923.jpg
We're dead excited this year to be welcoming members of the ...
Just a short announcement that this year's RetCon event is taking place on Saturday May 31st in West London - details and ticket sales available via the links further below.
IMG_20250511_131923.jpg
We're dead excited this year to be welcoming members of the ...
- Sun May 04, 2025 10:53 pm
- Forum: Hardware
- Topic: Minerva Mk2 Remake
- Replies: 61
- Views: 8172
Re: Minerva Mk2 Remake
Hi t0nyt!
I'm not sure which version appears on the GitHub I'm afraid, but by default, the upper 16KB of the ROM memory space is mapped -out- in the Minerva MK2 carrier board, thus allowing other devices to use the ext ROM slot. Therefore, if you leave the standard pin connections in place (pin 6 ...
I'm not sure which version appears on the GitHub I'm afraid, but by default, the upper 16KB of the ROM memory space is mapped -out- in the Minerva MK2 carrier board, thus allowing other devices to use the ext ROM slot. Therefore, if you leave the standard pin connections in place (pin 6 ...
- Fri May 02, 2025 12:53 am
- Forum: General QL Chat
- Topic: My current QL accelerator project
- Replies: 47
- Views: 4936
Re: My current QL accelerator project
Hi Will!
A bit of back of the envelope arithmetic and your accelerator seems to be pushing just under 900KB per second to screen memory.
Compare that to the (nominal, uncontended) max bus rate of a 7.5MHz QL of less than 2MB per sec - about half that to contended screen memory - and your ...
A bit of back of the envelope arithmetic and your accelerator seems to be pushing just under 900KB per second to screen memory.
Compare that to the (nominal, uncontended) max bus rate of a 7.5MHz QL of less than 2MB per sec - about half that to contended screen memory - and your ...
- Mon Apr 28, 2025 10:42 pm
- Forum: Software & Programming
- Topic: Talent 3D Designer
- Replies: 91
- Views: 28252
Re: Talent 3D Designer
Happy Birthday, Steve!
Now, I just need to find some time to explore your amazing 3D simulations and games!
Now, I just need to find some time to explore your amazing 3D simulations and games!
- Mon Apr 28, 2025 12:46 am
- Forum: Hardware
- Topic: [Solved] SOS My QL is dying
- Replies: 10
- Views: 663
Re: SOS My QL is dying
Hi there!
With regard to DSMCL remaining high - bear in mind that this signal, in the absence of anything holding it high, is merely a resistor-coupled DSL as generated by the CPU itself.
You might want to measure DSL directly to see whether or not it too is stuck inactive/high.
On the Iss6/7 ...
With regard to DSMCL remaining high - bear in mind that this signal, in the absence of anything holding it high, is merely a resistor-coupled DSL as generated by the CPU itself.
You might want to measure DSL directly to see whether or not it too is stuck inactive/high.
On the Iss6/7 ...
- Wed Apr 23, 2025 9:59 pm
- Forum: General QL Chat
- Topic: Wondering if a "dead test" ROM is feasible on the QL.
- Replies: 29
- Views: 1582
Re: Wondering if a "dead test" ROM is feasible on the QL.
Hi all!
Just to add/highlight - a working ZX8301 is essential - it delivers both the Clock to the CPU and also manages the DTACK line, without which, the CPU will never recognise a complete bus transaction and remain in limbo...
Still, I very much like the idea behind the original question!
Just to add/highlight - a working ZX8301 is essential - it delivers both the Clock to the CPU and also manages the DTACK line, without which, the CPU will never recognise a complete bus transaction and remain in limbo...
Still, I very much like the idea behind the original question!
- Mon Apr 14, 2025 6:34 pm
- Forum: Software & Programming
- Topic: My "from PACKAGE import *" (Python) simulation project (reflection)
- Replies: 37
- Views: 2611
Re: My "from PACKAGE import *" (Python) simulation project
Hi Peter
If you wish to stick to vanilla SuperBasic, then the following approach will work for any valid SuperBASIC program file:
1. Open the file with OPEN_IN as usual
2. Iterate through all its lines in a REPeat loop, INPUTing each one sequentially in to a variable, say lastLine$
3. Test before ...
If you wish to stick to vanilla SuperBasic, then the following approach will work for any valid SuperBASIC program file:
1. Open the file with OPEN_IN as usual
2. Iterate through all its lines in a REPeat loop, INPUTing each one sequentially in to a variable, say lastLine$
3. Test before ...
- Fri Apr 11, 2025 12:00 pm
- Forum: Hardware
- Topic: QLion Gold Card
- Replies: 84
- Views: 11308
Re: QLion Gold Card
Hi Leon!
I have good and bad news to report.
The bad news is that after the aurora modes and speed improvements QLion is no longer compatible with microdrives.
I may be able to give you a head-start there, as I had to rewrite some of the core MDV primitives (taken from Minerva) when I ...
I have good and bad news to report.
The bad news is that after the aurora modes and speed improvements QLion is no longer compatible with microdrives.
I may be able to give you a head-start there, as I had to rewrite some of the core MDV primitives (taken from Minerva) when I ...
- Mon Apr 07, 2025 11:12 pm
- Forum: General QL Chat
- Topic: My current QL accelerator project
- Replies: 47
- Views: 4936
Re: My current QL accelerator project
Hi Will
Ah yes, the buffering, that makes sense. However, I was expecting at least DTACK to have some activity because I read somewhere the QL
Video circuit holds the bus by keeping DTACK low during an access...
I suppose the whole circuit could be messed up by not having any pull ups in place ...
Ah yes, the buffering, that makes sense. However, I was expecting at least DTACK to have some activity because I read somewhere the QL
Video circuit holds the bus by keeping DTACK low during an access...
I suppose the whole circuit could be messed up by not having any pull ups in place ...